1. Field
The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly, to a semiconductor memory device including alternately stacked insulation layers and conductive layers, and a method of manufacturing the semiconductor memory device.
2. Discussion of Related Art
Various technologies capable of improving a degree of integration have been developed in a field of a semiconductor memory device. A 3D semiconductor memory device in which memory cells are three-dimensionally arranged on a substrate has been suggested as one of the technologies suggested for improvement of a degree of integration.
FIGS. 1A to 1D are cross-sectional views for describing a method of manufacturing a 3D semiconductor memory device in the related art.
Referring to FIG. 1A, a plurality of first material layers 11A to 11E and a plurality of second material layers 13A to 13D are alternately stacked. Each of the plurality of first material layers 11A to 11E may be formed on a layer on which an interlayer insulation layer is to be formed, and may be formed of an insulation material for the interlayer insulation layer. Each of the plurality of second material layers 13A to 13D may be formed on a layer on which a conductive pattern (for example, a word line or a select line) is to be formed, and may be formed as a material layer having high etching selectivity for the first material layers 11A to 11E. The plurality of second material layers 13A to 13D may be formed as first sacrificial layers.
Next, channel holes 21 are formed by etching the plurality of first material layers 11A to 11E and the plurality of second material layers 13A to 13D. Then, a memory layer 23 may be formed on a sidewall of each of the channel holes 21. Subsequently, channel layers 25 are formed in the channel holes 21 in which the memory layers 23 are formed.
Then, a trench 31 is formed by etching the plurality of first material layers 11A to 11E and the plurality of second material layers 13A to 13D between the channel layers 25. The trench 31 is formed so as to enable the sidewalls of the plurality of second material layers 13A to 13D to be exposed.
Referring to FIG. 1B, the plurality of second material layers 13A to 13D is selectively removed by an etching process using the large etching selectivity between the first material layers 11A to 11E and the plurality of second material layers 13A to 13D. A recess 41 is formed in each of regions in which the plurality of second material layers 13A to 13D is removed.
Referring to FIG. 1C, a conductive layer 51 is formed so as to fill the recess 41. A void 53 may be formed in the recess 41 during a process of forming the conductive layer 51.
Referring to FIG. 1D, a part of the conductive layer 51 formed in the trench 31 is removed by an etching process so that the conductive layer 51 is left only in the recess 41. Accordingly, a conductive pattern 51P separated for each recess 41 is formed.
In FIG. 1C, the conductive layer 51 may not be formed in a uniform thickness during the aforementioned process of forming the conductive layer 51. Further, an etching thickness may be non-uniform for each region during a process of etching the conductive layer 51. Accordingly, the void 53 in the recess 41 may be opened during the process of etching the conductive layer 51. More severely, an etching material permeates through the void 53 so that the conductive layer 51 in the recess 41 is completely removed, and thus the conductive pattern 51P in the recess 41 may not be left. When the etching thickness of the conductive layer 51 is decreased in order to decrease loss of the conductive pattern 51P, a defect that the conductive layer 51 is not separated for each recess 41 may be generated.
Due to the aforementioned problems, a level of difficulty of manufacturing a structure in which insulation layers and conductive layers are alternately stacked is increased.